Example embodiments relate to methods of forming recessed channel array transistors, and methods of manufacturing semiconductor devices.
As semiconductor devices may have been highly integrated, a gate length of a MOS transistor may be gradually decreased. Further, in order to improve an operational speed and a current drive capacity of the semiconductor device, a channel length of the semiconductor device may be reduced to deep sub-micron. Therefore, a short channel effect may be frequently generated in the MOS transistor due to a small size of the semiconductor device. This may cause a malfunction of a gate in the MOS transistor.
In order to solve the above-mentioned problems, recessed channel array transistors have been proposed. The recessed channel array transistors may have a long channel length by forming a recessed portion in a channel region of the MOS transistor. However, in the recessed channel array transistor, a gate insulating layer may be interposed between source/drain regions and a gate electrode. The source/drain regions may have a portion having large area confronting the gate electrode. This may cause a large gate induced leakage current.
Further, an electric field may be concentrated on an edge of the gate electrode. The edge of the gate electrode may function as a parasitic transistor that may cause a double bump where a turn-on may be generated twice.